The invention relates to high speed, high accuracy subranging analog-to-digital converters, and particularly to techniques for improving the accuracy of the residue signals thereof, simplifying the digital error correction circuitry, preventing overdrivng of the residue signal amplifiers, and improving the accuracy of the sample and hold input stages.
A type of analog-to-digital converter (ADC) known as a subranging ADC is one of three common types of high speed ADCs. ADCs of the successive approximation type are imple in structure, and may be very accurate, but they have very slow conversion times, due to the serial nature of the conversion processes therein. For example, for a successive approximation analog-to-digital converter with 12 bits of resolution, conversion times of about 0.6 microseconds to one microsecond are typical. At the other extreme, ADCs of the "flash converter" type have very short conversion times, requiring one cycle of operation. However, the high speed is achieved at the expense of greatly increased circuit complexity. Flash converters with 8 bits of resolution and conversion rates as high as 100 megahertz represent the limits of present integrated circuit technology. ADCs of the subranging type provide an intermediate compromise between flash encoders and successive approximation ADCs. The present state-of-the-art for subranging ADCs is thought to be represented by a 12 bit, 10 megahertz subranging analog-to-digital converter Model No. CAV-1210, manufactured by Analog Devices Corporation. Subranging analog-to-digital converters typically use a sample and hold or track and hold circuit that produces a sample voltage which is encoded by a MSB (most significant bit) flash encoder to produce an MSB word. The MSB word is temporarily stored in a register. The sampled analog input is also fed forward through a delay circuit to a summing node, that can also be referred to as a subtraction node. The MSB word then is input to a high acy digital-to-analog converter to produce a highly accurate analog representation of the MSB word, which then is subtracted from the fed forward analog input to produce a residue signal. The residue signal is amplified and applied to an LSB (least significant bit) flash encoder. The LSB word and the MSB word are combined by digital error correcting circuitry to produce the desired digital output word.
The most advanced presently available subranging ADCs suffer from a number of shortcomings. They are very expensive, typically costing about $2,500.00 for a 12 bit, 10 megahertz device. They typically are very large, requiring a 35 square inch printed circuit board. Their accuracy is likely to be less than their 12 bit resolution, and their reliability at speeds approaching the limit of their 10 megahertz specifications may be undesirably low. A relatively large number of external potentiometers, which must individually adjusted to obtain reasonably accurate conversion, add to the cost and inconvenience of presently available subranging ADCs. Adjustments of the external potentiometers at one temperature to achieve satisfactory operation at one temperature may not result in satisfactory operation at other temperatures.
Thus, it is clear that there is an unmet need for a very substantial improvement in the state-of-the-art of subranging analog-to-digital converters. However, the way to achieve such improvement has not been clear. There are many refinements that could enter into the overall performance of a subranging analog-to-digital converter, including refinements in the sample and hold or track and hold circuitry, improvements in the flash encoders used, different combinations of "widths" for the outputs of the MSB flash encoders and the LSB flash encoders, refinements for preventing overdriving of the residue amplifiers, and providing of different techniques and improvements in the digital error correcting circuitry for reconstructing the MSB word and the LSB word to produce an accurate digital output word of the desired resolution and accuracy.
The sample and hold circuits required in subranging analog-to-digital converters must be very accurate. Typically, such sample and hold (or track and hold) circuits include a switching diode sampling bridge that is isolated from the analog input signal by a high speed, highly accurate open loop input buffer. A sampling capacitor is connected to the output of the diode sampling bridge, which is actuated in response to a "sample command", and is applied as an input to a second high speed buffer. Typically, the output impedance of a sample and hold circuit of the type used in subranging analog-to-digital converters, such as the HTS0010 track and hold circuit made by Analog Devices Corporation, is about 5 ohms. The gain of the track and hold circuit is adjusted by an external potentiometer.
Although use of feedback amplifiers to achieve high input impedance and low output impedance is a common expedient, up to now no operational amplifier has been known having the very low input offset voltage, the high degree of temperature stability, the high input impedance, and the high bandwidth that would be needed to allow use of a closed loop output stage for a sample and hold (or track and hold) circuit that would be suitable for a 12 bit, 10 megahertz subranging analog-to-digital converter.